[PATCH] D129207: [X86] isTargetShuffleEquivalent - attempt to match SM_SentinelZero shuffle mask elements using known bits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 443286.
RKSimon added a comment.

fixed signed/unsigned mismatch


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129207/new/

https://reviews.llvm.org/D129207

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/pr51615.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining.ll
  llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll

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