[PATCH] D129207: [X86] isTargetShuffleEquivalent - attempt to match SM_SentinelZero shuffle mask elements using known bits
    Amaury SECHET via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Fri Jul  8 07:31:30 PDT 2022
    
    
  
deadalnix added inline comments.
================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:11795
+      SDValue ExpectedV = ExpectedIdx < Size ? V1 : V2;
+      if (ExpectedV && ExpectedV.getValueType().getVectorNumElements() == Size) {
+        int BitIdx = ExpectedIdx < Size ? ExpectedIdx : (ExpectedIdx - Size);
----------------
signed/unsigned comparison.
Repository:
  rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129207/new/
https://reviews.llvm.org/D129207
    
    
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