[PATCH] D120481: [AArch64] Try to re-use extended operand for SETCC with v16i8 operands.

Wed Jul 6 04:21:36 PDT 2022

dmgreen added a comment.

This sounds good as far as I can tell. If we are dealing with a dag combine, do we need to worry about odd types at all? And I think we can include eq and ne too, if alive is to be believed.

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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18043
+  EVT UseMVT = FirstUse->getValueType(0);
+  if (UseMVT.getScalarType().getScalarSizeInBits() <=
+      Op0MVT.getScalarType().getScalarSizeInBits())
----------------
I think this can skip the getScalarType call: UseMVT.getScalarSizeInBits() <= Op0MVT.getScalarSizeInBits()

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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18065
+                                        Op->getOperand(0));
+  if (Op0SExt && isSignedIntSetCC(CC)) {
+    Op0ExtV = SDValue(Op0SExt, 0);
----------------
Could these include eq and ne conditions too?

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Comment at: llvm/test/CodeGen/AArch64/vselect-ext.ll:157
 define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2(<8 x i16> %a) {
 ; check-label: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2:
 ; check:       ; %bb.0:
----------------
Can you remove all of these with the lower cases.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120481/new/

https://reviews.llvm.org/D120481