[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (shl (sext_inreg X, i32), C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 441177.
craig.topper added a comment.

Fix mistake in comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128843/new/

https://reviews.llvm.org/D128843

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

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