[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (shl (sext_inreg X, i32), C).

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 29 14:53:18 PDT 2022


craig.topper updated this revision to Diff 441177.
craig.topper added a comment.

Fix mistake in comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128843/new/

https://reviews.llvm.org/D128843

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D128843.441177.patch
Type: text/x-patch
Size: 3927 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220629/dbf96a7d/attachment.bin>


More information about the llvm-commits mailing list