[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (shl (sext_inreg X, i32), C).

Alex Bradbury via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 30 07:21:07 PDT 2022

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asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128843/new/

https://reviews.llvm.org/D128843

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