[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (shl (sext_inreg X, i32), C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8533
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+// Combine (sra (shl X, 32), 32 - C) -> (sra (sext_inreg X, i32), C)
+// FIXME: Should this be a generic combine? There's a similar combine on X86.
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I typoed this comment


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https://reviews.llvm.org/D128843