[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (sra (sext_inreg X, i32), C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I'm probably going to end up relaxing the one use check here to be that all users of the shl X, 32 are SRA instructions so that we can end up with a sext_inreg shared by multiple shls.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D128843/new/

https://reviews.llvm.org/D128843