[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (sra (sext_inreg X, i32), C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

My plan had been to solve https://godbolt.org/z/hssn6sPco by adding a fold for (add (shl X, 32), C<<32) -> (shl (add X, C), 32) and then let this patch optimize the shift with sra that might be after it. I thought the (add (shl X, 32), C<<32) fold could stand on its own as well, but in testing I found that some values of C cause an infinite loop with isDesirableToCommuteWithShift.

The larger (sra (add (shl X, 32), C << 32), 32-C1) -> (shl (sext_inreg (add X, C), i32), C1 <https://reviews.llvm.org/C1>) pattern is probably always profitable since the sext_inreg will always becomes an ADDW.


Repository:
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  https://reviews.llvm.org/D128843/new/

https://reviews.llvm.org/D128843