[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (sra (sext_inreg X, i32), C).
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 29 13:00:41 PDT 2022
craig.topper updated this revision to Diff 441138.
craig.topper added a comment.
Add FIXME to make this generic.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128843/new/
https://reviews.llvm.org/D128843
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
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