[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (sra (sext_inreg X, i32), C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D128843#3620025 <https://reviews.llvm.org/D128843#3620025>, @jrtc27 wrote:

> Given this only deals with generic nodes, would this make sense to be a TLI-guided generic combine? (And maybe other targets could benefit from it, too, or already do this in target combines?)

Looks like X86 has something similar in combineShiftRightArithmetic, but they handle a more generic form.

  // fold (ashr (shl, a, [56,48,32,24,16]), SarConst)                            
  // into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or                      
  // into (lshr, (sext (a), SarConst - [56,48,32,24,16]))                        
  // depending on sign of (SarConst - [56,48,32,24,16])  

For RISC-V we also support sext_inreg for i8 and i16 with Zbb. I'm not sure we want to convert to it naively since it won't always fold away and zext.h/zext.b aren't compressible. It probablys makes sense to convert i8/i16 if the input is a load even without Zbb. But that probably needs to create a sextload instead of creating a sext_inreg.

I have another patch I'm working on that depends on this one. So I'd like to consider making this target independent as a future pass. I'll add a FIXME.


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