[PATCH] D128758: [RISCV] Refine known bits for READ_VLENB

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9395
+    const unsigned MaxVLenB = Subtarget.getRealMaxVLen() / 8;
+     if (MinVLenB > 0)
+       Known.Zero.setLowBits(Log2_32(MinVLenB));
----------------
craig.topper wrote:
> Is every possible for this to be zero. I would think you'd need a READ_VLENB to be generated with all vector extensions disabled.
I agree.  Are you absolutely sure that's not possible?  I wasn't, and thus left the guard.  I can turn it into an assert if you prefer.  


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128758/new/

https://reviews.llvm.org/D128758