[PATCH] D128758: [RISCV] Refine known bits for READ_VLENB

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9395
+    const unsigned MaxVLenB = Subtarget.getRealMaxVLen() / 8;
+     if (MinVLenB > 0)
+       Known.Zero.setLowBits(Log2_32(MinVLenB));
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Is every possible for this to be zero. I would think you'd need a READ_VLENB to be generated with all vector extensions disabled.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9399
+    if (MaxVLenB == MinVLenB)
+      Known = KnownBits::makeConstant(APInt(BitWidth, MinVLenB));
     break;
----------------
reames wrote:
> craig.topper wrote:
> > Just to make sure I understand, given the Known.Zero that was already done. This is equivalent to Known.One.setBit(Log2_32(MinVLenB))?
> Yep, would you prefer I write it that way?  
Yeah. Let's write it that way.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128758/new/

https://reviews.llvm.org/D128758