[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:267
+  // Skip if it is an entry function or the register is already added.
+  if (isEntryFunction() || WWMVGPRs.count(VGPR))
+    return;
----------------
arsenm wrote:
> I don't understand why you would encounter the same register twice. This should assert the insert is a new insert?
The main place where we call this function is from `determineCalleeSaves` where we walk through each BB and identify every WRITELANE instruction. They will appear multiple times for different SGPR spills to separate lanes of the same register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192