[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:485
+  SmallVector<Register, 2> SpillVGPRs;
+  using WWMVGPRsMap = MapVector<Register, Optional<int>>;
+  // To track the registers used in instructions that can potentially modify the
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Why is the frame index optional? The only case where you wouldn't have this is the entry function case, where you skip the insertion. It might be clearer to make this non-optional and rename to WWMSpills


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  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192