[PATCH] D128286: [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb accepted this revision.
arcbbb added a comment.
This revision is now accepted and ready to land.

It's great that `MinElts` can be obtained from `RISCV::RVVBitsPerBlock / Subtarget.getELEN()`
LGTM. Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128286/new/

https://reviews.llvm.org/D128286