[PATCH] D128144: [AArch64] Known bits for AArch64ISD::DUP

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:1866
 
+  virtual bool isCanonicalConstantNode(unsigned Opc, EVT VT) const {
+    return Opc == ISD::SPLAT_VECTOR;
----------------
Add doxygen comment


================
Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:1867
+  virtual bool isCanonicalConstantNode(unsigned Opc, EVT VT) const {
+    return Opc == ISD::SPLAT_VECTOR;
+  }
----------------
Does this mean we can/should add ISD::SPLAT_VECTOR handling to TargetLowering::SimplifyDemandedBits ?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.h:1151
+  bool isCanonicalConstantNode(unsigned Opc, EVT VT) const override {
+    return Opc == ISD::SPLAT_VECTOR || Opc == AArch64ISD::DUP;
+  }
----------------
We probably want to do something like this in case this gets extended in the future:
```
return Opc == AArch64ISD::DUP || TargetLoweringBase::isCanonicalConstantNode(Opc, VT);
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128144/new/

https://reviews.llvm.org/D128144