[PATCH] D128144: [AArch64] Known bits for AArch64ISD::DUP

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:1867
+  virtual bool isCanonicalConstantNode(unsigned Opc, EVT VT) const {
+    return Opc == ISD::SPLAT_VECTOR;
+  }
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RKSimon wrote:
> Does this mean we can/should add ISD::SPLAT_VECTOR handling to TargetLowering::SimplifyDemandedBits ?
Yeah that sounds good, but we will need to enable SimplifyDemandedBits for scalable vectors first, which is in a followup patch. Enabling ComputeKnownBits for SPLAT_VECTOR is a part of D128159.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128144/new/

https://reviews.llvm.org/D128144