[PATCH] D128023: [RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 16 19:38:54 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: reames, frasercrmck, rogfer01, kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
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craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
Use it in place of VSELECT_VL+VRGATHER*_VL.
This simplifies the isel patterns.
Overall, I think trying to match select+op to create masked instructions
in isel doesn't scale. We either need to do it in DAG combine, pre-isel
peepole, or post-isel peephole. I don't yet know which is the right
answer, but for this case it seemed best to be able to request the
masked form directly from lowering.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128023
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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