[PATCH] D128023: [RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Seems reasonable to me, it is hard to see how select+op patterns could ever scale on large ISA like this. I've done a post-isel MIR peephole for this sort of thing in the past. We could perhaps also do a DAG post-process like we do for masked/unmasked RVV.

On the patch: we probably need to update the ISD opcode comment in RISCVISelLowering.h? We do comment passthru/merge operands though I don't know if our coverage is 100%.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1841
                 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
-  def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
+  def : Pat<(vti.Vector (riscv_vrgather_vv_vl (vti.Vector srcvalue),
+                                              vti.RegClass:$rs2,
----------------
I'm a bit out of the loop, but could the DAG post-process turn masked vrgathers into unmasked ones? Could we remove the `true_mask` patterns while we're at it?


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