[llvm] 16215eb - [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCV

[Lian Wang via llvm-commits]

Author: Lian Wang
Date: 2022-06-17T02:26:09Z
New Revision: 16215eb9790ac47e1f628ec7fdcb237df0adbb23

URL: https://github.com/llvm/llvm-project/commit/16215eb9790ac47e1f628ec7fdcb237df0adbb23
DIFF: https://github.com/llvm/llvm-project/commit/16215eb9790ac47e1f628ec7fdcb237df0adbb23.diff

LOG: [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCV

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D127939

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/test/CodeGen/RISCV/rvv/stepvector.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index a4198c4329f78..4df73e67e0141 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -5277,7 +5277,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
   SDLoc dl(N);
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
-  assert(NOutVT.isVector() && "Type must be promoted to a vector type");
+  assert(NOutVT.isScalableVector() &&
+         "Type must be promoted to a scalable vector type");
   APInt StepVal = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
   return DAG.getStepVector(dl, NOutVT,
                            StepVal.sext(NOutVT.getScalarSizeInBits()));

diff  --git a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
index 61e1386503b4f..e94a8a432eaef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
@@ -167,6 +167,18 @@ define <vscale x 2 x i16> @stepvector_nxv2i16() {
   ret <vscale x 2 x i16> %v
 }
 
+declare <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15()
+
+define <vscale x 2 x i15> @stepvector_nxv2i15() {
+; CHECK-LABEL: stepvector_nxv2i15:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    ret
+  %v = call <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15()
+  ret <vscale x 2 x i15> %v
+}
+
 declare <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16()
 
 define <vscale x 3 x i16> @stepvector_nxv3i16() {
@@ -515,7 +527,6 @@ entry:
   ret <vscale x 8 x i64> %3
 }
 
-
 define <vscale x 8 x i64> @shl_stepvector_nxv8i64() {
 ; CHECK-LABEL: shl_stepvector_nxv8i64:
 ; CHECK:       # %bb.0: # %entry