[llvm] 5e16a78 - [RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll

[Lian Wang via llvm-commits]

Author: Lian Wang
Date: 2022-06-17T02:22:59Z
New Revision: 5e16a781bada1f8ef7e1045bafd584c59ec554b9

URL: https://github.com/llvm/llvm-project/commit/5e16a781bada1f8ef7e1045bafd584c59ec554b9
DIFF: https://github.com/llvm/llvm-project/commit/5e16a781bada1f8ef7e1045bafd584c59ec554b9.diff

LOG: [RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll

Reviewed By: victor-eds, frasercrmck

Differential Revision: https://reviews.llvm.org/D127946

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
index 6802c5d48cfe6..36032be8d41a7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -315,7 +315,7 @@ define double @vpreduce_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscal
   ret double %r
 }
 
-define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_ord_fadd_nxv3f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
@@ -324,11 +324,10 @@ define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 4 x double> %v, <v
 ; CHECK-NEXT:    vfredosum.vs v12, v8, v12, v0.t
 ; CHECK-NEXT:    vfmv.f.s fa0, v12
 ; CHECK-NEXT:    ret
-  %r = call double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)
+  %r = call double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)
   ret double %r
 }
 
-
 declare double @llvm.vp.reduce.fadd.nxv4f64(double, <vscale x 4 x double>, <vscale x 4 x i1>, i32)
 
 define double @vpreduce_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {