[PATCH] D127848: [CodeGen] Fix the bug of machine sink

Wed Jun 15 08:51:04 PDT 2022

LuoYuanke added a comment.

In D127848#3585696 <https://reviews.llvm.org/D127848#3585696>, @MatzeB wrote:

> I'm also not sure right now if vregs without definitions are even legal MIR while we are still in MachineSSA... Checking that now

Sorry, I merged it in a rush. We can revert it and add assert for nullptr if undef value is illegal in MIR.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127848/new/

https://reviews.llvm.org/D127848