[PATCH] D127721: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


================
Comment at: llvm/test/MC/RISCV/rv64zdinx-invalid.s:4
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
----------------
I guess you probably want `fld` and `fsd` ?


================
Comment at: llvm/test/MC/RISCV/rv64zfh-invalid.s:12
+fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
 # Integer registers where FP regs are expected
----------------
also add `invalid operand` for `fld`/`fsd` along with `fsw`/`flw` ?


================
Comment at: llvm/test/MC/RISCV/rv64zhinx-invalid.s:4
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
----------------
I guess you want `flh`/`fsh` ? 


================
Comment at: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s:4
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
----------------
I guess you want `flh`/`fsh` ? 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127721/new/

https://reviews.llvm.org/D127721