[PATCH] D127721: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s

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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127721

Files:
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zfh-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s


Index: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,6 +1,10 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
 # Invalid instructions
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 
Index: llvm/test/MC/RISCV/rv64zhinx-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,6 +1,10 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
 # Invalid instructions
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 
Index: llvm/test/MC/RISCV/rv64zfinx-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv64zfinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zfinx-invalid.s
@@ -1,6 +1,10 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zfinx %s 2>&1 | FileCheck %s
 
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
 # Invalid instructions
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fmv.x.w t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.w.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 
Index: llvm/test/MC/RISCV/rv64zfh-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv64zfh-invalid.s
+++ llvm/test/MC/RISCV/rv64zfh-invalid.s
@@ -1,6 +1,15 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zfh < %s 2>&1 | \
 # RUN:   FileCheck %s
 
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
 # Integer registers where FP regs are expected
 fcvt.l.h ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv64zdinx-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv64zdinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zdinx-invalid.s
@@ -1,6 +1,10 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zdinx %s 2>&1 | FileCheck %s
 
-# Invalid Instructions
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
+# Invalid instructions
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fmv.x.d t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.d.x a5, t5 # CHECK: :[[@LINE]]:9:  error: invalid operand for instruction
 


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