[PATCH] D127642: [RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/undef-subreg-range.mir:1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -O2 -mtriple riscv64 -riscv-enable-subreg-liveness \
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Move to rvv directory since it uses RVV instructions?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127642/new/

https://reviews.llvm.org/D127642