[PATCH] D127642: [RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:318
+    // Adding implicit-use of super register to describe we are using part of
+    // super register, that prevent machine verifier complain when part of
+    // subreg is undef, see comment in MachineVerifier::checkLiveness for more
----------------
prevent -> prevents
complain -> complaining


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:325
+        .addMemOperand(*(MBBI->memoperands_begin()))
+        .add(
+            MachineOperand::CreateReg(SrcReg, /*isDef=*/false, /*isImp=*/true));
----------------
can this be `.addReg(SrcReg, RegState::Implicit)`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127642/new/

https://reviews.llvm.org/D127642