[PATCH] D127596: [AArch64][CodeGen] Support select address mode load/store

Mon Jun 13 07:35:47 PDT 2022

Allen added a comment.

In D127596#3577439 <https://reviews.llvm.org/D127596#3577439>, @paulwalker-arm wrote:

> I don't believe we want this functionality.  We originally added it but then it got removed by D88994 <https://reviews.llvm.org/D88994> as unsound because there's no instruction available to load/store predicates that are smaller than `<vscale x 16 x i1>`.  At the C/C++ level we don't expose these "smaller" predicate types and so there shouldn't really be a route needed to load/store them.  @Allen Do you have a real world use case where loading/storing them is required?

Thanks @paulwalker-arm very much, I don't have a C case. But only my colleague found that the case compilation failed and tried to rectify the fault.
You have a good memory to find this patch D88994 <https://reviews.llvm.org/D88994>, which helps me understand the problem, thanks again!

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https://reviews.llvm.org/D127596