[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added a comment.

In D124192#3534493 <https://reviews.llvm.org/D124192#3534493>, @nhaehnle wrote:

> I don't think the premise of this patch is correct. A source-level `writelane` intrinsic is **not** allowed to overwrite inactive lanes. If it does, then that's UB. If you want wave-wide `writelane` in source, the way to achieve that would be to use WWM.

Are you saying the usage of writelane intrinsic as specified in test `kernel_writelane_intrinsic` added with llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll doesn't really cause any inactive lane overwrite?
I remember having such usages being mentioned for a potential inactive lane overwrite issue.

Sorry about the late response (was behind a priority work).


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