[PATCH] D127596: [AArch64][CodeGen] Support select address mode load/store
Paul Walker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 13 04:00:36 PDT 2022
paulwalker-arm added a comment.
I don't believe we want this functionality. We originally added it but then it got removed by D88994 <https://reviews.llvm.org/D88994> as unsound because there's no instruction available to load/store predicates that are smaller than `<vscale x 16 x i1>`. At the C/C++ level we don't expose these "smaller" predicate types and so there shouldn't really be a route needed to load/store them. @Allen Do you have a real world use case where loading/storing them is required?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127596/new/
https://reviews.llvm.org/D127596
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