[PATCH] D127317: [AArch64][SME] Add ldr/str (fill/spill) intrinsics
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 9 01:08:29 PDT 2022
david-arm added inline comments.
================
Comment at: llvm/test/CodeGen/AArch64/SME/sme-intrinsics-loads.ll:265
+; CHECK-NEXT: ret
+ %base = getelementptr i8, i8* %ptr, i64 15
+ call void @llvm.aarch64.sme.ldr(i32 0, i8* %base)
----------------
aemerson wrote:
> I'm not following why a byte offset from a pointer would lower into an offset scaled by VL?
That's an excellent point @aemerson! Something has clearly gone wrong here - I'll investigate!
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127317/new/
https://reviews.llvm.org/D127317
More information about the llvm-commits
mailing list