[PATCH] D127317: [AArch64][SME] Add ldr/str (fill/spill) intrinsics

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:2351
+  MIB.add(MI.getOperand(2)); // base
+  MIB.add(MI.getOperand(1)); // offset, same as vector select offset
+
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Nit: Comments usually start with capitals.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:3210
+// (unsigned immediate)
+// Indexed for 8-bit registers. offset is in range [0,15].
+def am_indexed8_4b : ComplexPattern<i64, 2, "SelectAddrModeIndexedUImm<1,15>", []>;
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s/offset/Offset


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Comment at: llvm/test/CodeGen/AArch64/SME/sme-intrinsics-loads.ll:265
+; CHECK-NEXT:    ret
+  %base = getelementptr i8, i8* %ptr, i64 15
+  call void @llvm.aarch64.sme.ldr(i32 0, i8* %base)
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I'm not following why a byte offset from a pointer would lower into an offset scaled by VL?


Repository:
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  https://reviews.llvm.org/D127317/new/

https://reviews.llvm.org/D127317