[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

[yanming via Phabricator via llvm-commits]

ym1813382441 updated this revision to Diff 434387.
ym1813382441 added a comment.

Remove redundant conditions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126854/new/

https://reviews.llvm.org/D126854

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll

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