[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

[yanming via Phabricator via llvm-commits]

ym1813382441 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h:213
+    case RISCVRegisterClass::FPRRC:
+      if (ST->hasStdExtZfh() || ST->hasStdExtF() || ST->hasStdExtD())
         return 32;
----------------
kito-cheng wrote:
> Checking `F` is enough here since `Zfh` and `D` both implied `F`.
okey


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D126854/new/

https://reviews.llvm.org/D126854