[PATCH] D126884: [RISCV] Hoist vsetvli with vreg operand out of loops

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1330
+    // time impact was worthwhile.
+    if (DefMI->getParent()->instr_end() != InsertPt)
+      return;
----------------
craig.topper wrote:
> Does the end iterator of a basic block point a unique state such that this returning true means that DefMI is in UnavailablePred? Or could they both be at the end of different basic blocks?
They could be in different basic blocks, so there's an iterator comparison bug here.  Thanks!

Will rev with a fix.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126884/new/

https://reviews.llvm.org/D126884