[PATCH] D126884: [RISCV] Hoist vsetvli with vreg operand out of loops
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 2 22:07:50 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1330
+ // time impact was worthwhile.
+ if (DefMI->getParent()->instr_end() != InsertPt)
+ return;
----------------
Does the end iterator of a basic block point a unique state such that this returning true means that DefMI is in UnavailablePred? Or could they both be at the end of different basic blocks?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D126884/new/
https://reviews.llvm.org/D126884
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