[PATCH] D124612: [AArch64][LV] AArch64 does not prefer vectorized addressing

[Tiehu Zhang via Phabricator via llvm-commits]

TiehuZhang added a comment.

In D124612#3536665 <https://reviews.llvm.org/D124612#3536665>, @dmgreen wrote:

> Thanks for getting the numbers.

Thanks for the comment, @dmgreen ! 
This patch may affect the widening decision (**It actually affects ScalarizationCost**) in `setCostBasedWideningDecision` for these loads .  NEON cannot process vectorized addresses and requires `exectelement` support. Therefore, `ScalarizationCost` will add the overhead of this instruction (`3` x InterleaveGroupSize). After the patch, `ScalarizationCost` excludes this overhead, and the cost becomes smaller.

Before the patch:

  ScalarizationCost: {Value = 20, State = llvm::InstructionCost::Valid}
  InterleaveCost: {Value = 17, State = llvm::InstructionCost::Valid}
  Final Decision and Cost: CM_Interleave, 17

After the patch

  ScalarizationCost: {Value = 14, State = llvm::InstructionCost::Valid}
  InterleaveCost: {Value = 17, State = llvm::InstructionCost::Valid}
  Final Decision and Cost: CM_Scalarize, 14



================
Comment at: llvm/test/Transforms/LoopVectorize/AArch64/interleaved-vs-scalar.ll:13
 ; CHECK: vector.body
-; CHECK: load <4 x i8>
+; CHECK: load i8
 ; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
----------------
dmgreen wrote:
> dmgreen wrote:
> > It is hard to see why this is now correct.. the vector body looks pretty empty?
> Do you know what is going on in this case?
> Do you know what is going on in this case?




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