[PATCH] D126563: [RISCV] Allow PRE of vsetvli involving non-1 LMUL

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

There is an option to scale the LMUL returned to the vectorizer by TTI getRegisterBitWidth. Using that you can get LMUL>1 fixed vector loops. https://godbolt.org/z/34asbPcv7 should work for scalar too.


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https://reviews.llvm.org/D126563