[PATCH] D126563: [RISCV] Allow PRE of vsetvli involving non-1 LMUL

[Philip Reames via Phabricator via llvm-commits]

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This is a follow up to address a review comment from D124869 <https://reviews.llvm.org/D124869>.  When deciding whether to PRE a vsetvli, we can allow non-LMUL1 vsetvlis.

Despite posting this, I'm not sure we should land it.  I think it is correct, but it also appears to be dead code today.  All of the examples I've played with involving non-1 LMULs hit other problems first, and we never actually get to this.  Thoughts?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126563

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp


Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1283,14 +1283,17 @@
     // vreg def placement.
     return RISCV::X0 == Info.getAVLReg();
 
-  if (RISCVII::LMUL_1 != Info.getVLMUL())
-    // TODO: Generalize the code below to account for LMUL
-    return false;
-
   unsigned AVL = Info.getAVLImm();
   unsigned SEW = Info.getSEW();
   unsigned AVLInBits = AVL * SEW;
-  return ST.getRealMinVLen() >= AVLInBits;
+
+  unsigned LMul;
+  bool Fractional;
+  std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(Info.getVLMUL());
+
+  if (Fractional)
+    return ST.getRealMinVLen() / LMul >= AVLInBits;
+  return ST.getRealMinVLen() * LMul >= AVLInBits;
 }
 
 /// Perform simple partial redundancy elimination of the VSETVLI instructions


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