[PATCH] D126563: [RISCV] Allow PRE of vsetvli involving non-1 LMUL

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D126563#3543147 <https://reviews.llvm.org/D126563#3543147>, @craig.topper wrote:

> There is an option to scale the bitwidth returned to the vectorizer by TTI getRegisterBitWidth. Using that you can get LMUL>1 fixed vector loops. https://godbolt.org/z/34asbPcv7 should work for scalar too.

I had added some lmul fixed length tests to test/CodeGen/RISCV/rvv/sink-splat-operands.ll.  (Odd name, but it's where all of our non-lmul variants were, so...)

We seem to end up with odd patterns around loads and stores in the loop where we toggle back and forth between e8 and e32.  This toggling means we can't currently PRE.


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https://reviews.llvm.org/D126563