[PATCH] D125962: [RISCV] Add a test showing overlapping stack offsets with RVV

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD added a comment.

Hi @frasercrmck ,

May I ask why does the generated asm stores is trying to store `a0 (x10)`?
The RISC-V calling convention <https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf> specifies that `a0` is a caller saved register.

Regards,

eop Chen


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https://reviews.llvm.org/D125962