[PATCH] D125962: [RISCV] Add a test showing overlapping stack offsets with RVV

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D125962#3533712 <https://reviews.llvm.org/D125962#3533712>, @eopXD wrote:

> Hi @frasercrmck ,
>
> May I ask why does the generated asm stores is trying to store `a0 (x10)`?
> The RISC-V calling convention <https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf> specifies that `a0` is a caller saved register.
>
> Regards,
>
> eop Chen

Hi. The test is arbitrary and is storing `s9/$x25` just to have something storing to a scalar stack slot to exercise the frame lowering; it's not a real callee spill.

Since `$x25` is a copy of `a0/$x10`, eventually the machine copy propagation pass removes the copy and that's why it becomes a store of `a0`.

We could update the tests to use a callee-saved register for readability, but this isn't a correctness issue.


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