[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 10 08:35:44 PDT 2022

Previous message: [PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3
Next message: [PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

dmgreen added a comment.

Oh yeah, I missed that testcase. I'll revert for now. Thanks for the report.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782

Previous message: [PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3
Next message: [PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list