[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 10 08:35:44 PDT 2022
dmgreen added a comment.
Oh yeah, I missed that testcase. I'll revert for now. Thanks for the report.
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https://reviews.llvm.org/D123782/new/
https://reviews.llvm.org/D123782
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