[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[NAKAMURA Takumi via Phabricator via llvm-commits]

chapuni added a comment.

This causes miscompilation in llvm::lowertypetests::BitSetBuilder::build() in llvm/lib/Transforms/IPO/LowerTypeTests.cpp.
LLVM-Unit::IPOTests catches this.
BSI.AlignLog2 is masked by "and #0x1F".



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17698
+
+  unsigned BitWidth = CTTZ.getValueSizeInBits();
+  SDValue BitWidthMinusOne =
----------------
CTTZ may be ISD::TRUNCATE.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782