[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic added a comment.

@chapuni @dmgreen How do I trigger this unit test failure? When I run check-llvm-unit all the tests pass for me. I don't understand what I am missing here.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782