[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic added a comment.

In D123782#3493238 <https://reviews.llvm.org/D123782#3493238>, @dmgreen wrote:

> Other than the point @craig.topper mentioned, this Looks OK to me.

I have marked this as a child revision of https://reviews.llvm.org/D113291 but this patch should work independently of that. Should I remove that as a parent revision? Please let me know what you think (@djtodoro too). Additionally, how should I go about committing this since I don't have commit access?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782