[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu May 5 01:30:13 PDT 2022

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dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Other than the point @craig.topper mentioned, this Looks OK to me.


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  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782

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