[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17676
+
+  if (!isNullConstant(Zero) || !isNullConstant(SUBS.getValue(1).getOperand(1)))
+    return SDValue();
----------------
`SUB.getValue(1).getOperand(1)` can be shortened to `SUBS.getOperand(1)`. The Result number in isn't used by `SDValue::getOperand`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782