[PATCH] D124961: [riscv] Use X0 for destination of VSETVLI instruction if result unused

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D124961#3492285 <https://reviews.llvm.org/D124961#3492285>, @craig.topper wrote:

>> Since after the core insertion/lowering algorithm has run, basically all user written VSETVLIs will have their GPR result unused (as VTYPE/VLEN is now explicitly read instead), this kicks in for most tests which involve a vsetvli intrinsic. When inserting VSETVLIs to lower psuedos, we prefer the X0 form anyways.
>
> Almost any real scenario that processes more data than fits in a register will need the GPR output to update memory pointers and to control a loop. Which I guess means we're lacking realistic tests.

How so?  An idiomatic tail folded loop doesn't need to explicitly read VL.  It's passed via VL reg itself to all the vector ops.  It changes across iterations, but that doesn't mean the GPR is used.



================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1219
+      for (MachineInstr &MI : MBB) {
+        if (MI.getOpcode() == RISCV::PseudoVSETVLI) {
+          Register VRegDef = MI.getOperand(0).getReg();
----------------
craig.topper wrote:
> This is valid for VSETIVLI too.
True.  Will update.


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