[PATCH] D124961: [riscv] Use X0 for destination of VSETVLI instruction if result unused
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 4 14:01:37 PDT 2022
craig.topper added a comment.
> Since after the core insertion/lowering algorithm has run, basically all user written VSETVLIs will have their GPR result unused (as VTYPE/VLEN is now explicitly read instead), this kicks in for most tests which involve a vsetvli intrinsic. When inserting VSETVLIs to lower psuedos, we prefer the X0 form anyways.
Almost any real scenario that processes more data than fits in a register will need the GPR output to update memory pointers and to control a loop. Which I guess means we're lacking realistic tests.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1219
+ for (MachineInstr &MI : MBB) {
+ if (MI.getOpcode() == RISCV::PseudoVSETVLI) {
+ Register VRegDef = MI.getOperand(0).getReg();
----------------
This is valid for VSETIVLI too.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124961/new/
https://reviews.llvm.org/D124961
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