[PATCH] D124961: [riscv] Use X0 for destination of VSETVLI instruction if result unused

[Philip Reames via Phabricator via llvm-commits]

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If the GPR destination register of a VSETVLI instruction is unused, we can replace it with X0.  This discards the result, and thus reduces register pressure.

Since after the core insertion/lowering algorithm has run, basically all user written VSETVLIs will have their GPR result unused (as VTYPE/VLEN is now explicitly read instead), this kicks in for most tests which involve a vsetvli intrinsic.  When inserting VSETVLIs to lower psuedos, we prefer the X0 form anyways.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124961

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

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